This invention relates to a semiconductor device and a method of manufacturing the same, more particularly to a construction of a doped polycrystalline silicon region formed on a semiconductor or an insulation substrate, an insulation isolating structure between the doped polycrystalline silicon region and another regions, a bipolar transistor utilizing the doped polycrystalline silicon region, a junction type field effect transistor and a method of manufacturing the same.
Recent efforts in the development of IC semiconductor technique have been concentrated in the area of increasing the density of the integrated circuits, improving the performance of such circuits simplifying the manufacturing steps for such circuits. To attain these objects it has been proposed to variously change combinations of a polycrystalline semiconductor layer and a semiconductor substrate or such insulating films as SiO.sub.2 and Si.sub.3 N.sub.4 films to be formed on the semiconductor substrate. However, each of these combinations is not yet perfect and for long years it has been desired to develop semiconductor devices and methods of manufacturing the same capable of improving the density, and the performance and simplifying the manufacturing process.
For a better understanding of the invention, one prior art technique will be described hereunder. For example, consider a case wherein an insulating film such as a SiO.sub.2 film, is formed on a silicon substrate, and a wiring layer comprising a polycrystalline silicon layer is formed on the insulating film, or an electrode of a transistor is formed on the substrate. One prior art method comprises the steps of forming a polycrystalline silicon layer on the insulating film, depositing a photoresist on the polycrystalline silicon layer and then chemically etching off unnecessary portions of the polycrystalline silicon layer by using the photoresist. In the case of a polycrystalline silicon doped with boron at a density of about 10.sup.21 atoms/cm.sup.3, an etchant consisting of HF:HNO.sub.3 :H.sub.2 O=1:20:20 is suitable. With this method, however, the spacing between adjacent wiring layers or electrodes and the substrate is determined by a minimum gap that permits formation of a photoresist pattern. This minimum gap is generally of the order of 3 microns. For this reason, when a transistor is prepared with this method not only is the base resistance relatively large, but also the parasitic collector-base capacitance is also large. Where the polycrystalline silicon layer is worked with only chemical etching, the portions of the polycrystalline silicon layer underlying the photoresist and which should be retained to form a wiring layer or an electrode would be etched off (side etching) with the result that the spacing between adjacent wiring layers would become larger than expected. Moreover, due to the effect of the side etching, the cross-sectional configuration becomes a mesa which has a smaller area than expected, thus limiting the current capacity of the wiring layer.
According to another prior art method, the polycrystalline silicon layer on the oxide film is etched off with plasma by using a photoresist pattern disposed on the polycrystalline silicon layer as disclosed in J. Electrochem. Soc.: "Solid-State Sience and Technology", May 1978, Vol. 125 No. 5, page 827-828. With this method, the polycrystalline silicon layer would be worked to have a desired mask configuration, that is to cause the cross-sectional configuration of the wiring pattern to have a rectangular configuration as determined by the photoresist pattern. Similar to the chemical etching, the spacing to the adjacent wiring layer, however, is determined by the working accuracy of the photoresist so that the minimum gap is of the order of about 3 microns. Moreover, as the edges of the wiring layer are sharp, there is a fear of breaking the layer or wires by such sharp edges. The base resistance and the collector-base parasitic capacitance are also high as in the case of the chemical etching.
Still another prior art method comprises the steps of forming a layer of a material having a lower oxidizing speed than polycrystalline silicon, for example Si.sub.3 N.sub.4, and having a predetermined pattern on a polycrystalline silicon layer on an oxide film, selectively thermally-oxidizing the polycrystalline silicon layer so as to form an isolated region of the polycrystalline silicon layer, that is a wiring layer or an electrode. This method is disclosed in U.S. Pat. No. 4,074,304. However, this method presents the same problem as first described method.
According to yet another prior art method an insulating film is selectively formed on a polycrystalline silicon layer formed on an oxide film, and an impurity such as boron is diffused into a portion of the polycrystalline silicon layer not covered by the insulating film. The insulating film formed on the polycrystalline silicon layer is selectively removed and thereafter the portion of the polycrystalline silicon not containing the impurity is removed by using the difference in the etching speeds between the portions containing and not containing the impurity when a KOH type etchant is used. This method is disclosed, for example, in British Pat. No. 1,417,170.
According to this method, since the impurity selectively thermally-diffuses into the portion of the polycrystalline silicon layer under a selectively arranged insulating film, it is possible to form a wiring layer diffused with the impurity with closer interlead spacing (for example with a spacing of less than 2 microns) than those formed by various methods aforementioned. However, the wiring layer would have overhang edges which project toward adjacent wiring layers. Consequently, although the cross-sectional area of the wiring layer becomes larger but, using this method the sharp edges damage an insulating layer or a wiring layer formed thereon.
Where a transistor is prepared according to one of many well known methods, it is necessary to use at least four photoetching steps for forming a base diffusion opening, an emitter diffusion window, a base electrode lead window and an electrode forming window and it is necessary to use various photomask patterns for defining the contour of respective performance regions. For this reason, in order to produce a high density and high performance transistor, it is necessary to align the respective photoetching positions and to work at a high degree of accuracy. This decreases the yield, making it difficult to obtain extremely precise transistors.
To solve these problems we have already proposed a method as disclosed in our copending U.S. patent application Ser. No. 898,074 filed on Apr. 20, 1978.
In a transistor disclosed therein, a base electrode comprising a polycrystalline layer having a constant width is disposed adjacent a boundary and around the entire periphery of a base region surface formed on a semiconductor substrate and having a base contact about the periphery, an emitter electrode comprising polycrystalline silicon is formed on the surface of an island-shaped emitter region formed in the base region, and the base and emitter electrodes are electrically isolated by an insulating film.
With this construction, however, when forming the emitter electrode wherein a polycrystalline silicon layer is provided beneath the emitter electrode for the purpose of stabilizing the electrode for a thin emitter junction, the polycrystalline silicon layer is required to completely cover the emitter region so that it is necessary to increase the peripheral dimension of the emitter region by taking into consideration a position aligning allowance. This hinders manufacture of extremely fine transistors. Further, with this construction, it is necessary to determine the position of the emitter-base junction at a portion which is in contact with the insulating film of a small width and serves to isolate the base electrode from the emitter electrode so that the position of the side junction of the emitter electrode is determined according to the relationship between the depth of the base contact region and the emitter depth. This determines the insulating strength between the emitter and base electrodes and since the breakdown voltage is determined by controlling the lateral dispersion, the electrical characteristics of the resulting transistors are not always uniform. With this construction, the side wall of the emitter electrodes comprises a p-n junction between regions each having a high impurity concentration, thus increasing the parasitic capacitance and decreasing f.sub.T. Moreover, according to this construction, the emitter electrode is formed as a fourth layer with respect to the substrate thus complicating the manufacturing steps of such multilayer construction and rendering it difficult to obtain high density integrated circuits.